LSISASX12 LSI, LSISASX12 Datasheet - Page 72

no-image

LSISASX12

Manufacturer Part Number
LSISASX12
Description
Manufacturer
LSI
Datasheet

Specifications of LSISASX12

Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LSISASX12A
Manufacturer:
LSILOGIC
Quantity:
5 510
Part Number:
LSISASX12A
Manufacturer:
LT
Quantity:
5 510
3.6
Table 3.4
3-6
Signal Name
CBL_DET[11:0]/
LED_ACT[11:0]/
LED_FAULT[11:0]/
LED_STATUS[11:0]/ AF9, AF16,
RESET/
CLK
GPIO[3:0]
UART_TX
Configuration and General-Purpose Signals
Configuration and General-Purpose Signal Description
Table 3.4
signals.
Signal Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
BGA Position I/O
A5, A6, A7,
A8, C8, B8,
A16, D14,
B16, C16,
D15, E16
AD6, AC7,
AE6, AF5,
AF6, AF7,
AF21, AA18,
AF22, AE22,
AD22, AF23
AC9, AD9,
AE9, AB11,
AD10, AC12,
AE23, AF24,
AA20, AF25,
AB21, AD23
AF17, AF18,
AB15, AE18,
AD18, AE19,
AB17, AF19,
AF20, AB18
AD14
AE11
AC23, AE24,
AA21, AD24
F18
describes a possible configuration of the general-purpose
I/O
I/O
I/O
I/O
I
I
I/O
O
Description
The Cable Detection pins can be configured to detect the
presence of a cable on the associated phy. These pins
can also be configured as activity LEDs, fault LEDs, status
LEDs, or independent GPIO signals.
The Activity LED pins can be configured to indicate serial
port activity by driving an LED. These pins can also be
configured as cable detection LEDs, fault LEDs, status
LEDs, or independent GPIO signals.
The Fault LED pins can be configured to indicate a serial
port fault by driving an LED. These pins can also be
configured as cable detection LEDs, activity LEDs, status
LEDs, or independent GPIO signals.
The Status LED pins can be configured to indicate disk
drive activity by driving an LED. These pins can also be
configured as cable detection LEDs, activity LEDs, fault
LEDs, or independent GPIO signals.
LED_STATUS[11:6]/ are multiplexed to the SIO interface.
Refer to
SIO interface signal definitions.
Asserting the Reset pin (which is an active LOW signal)
forces the chip into a Power-On-Reset (POR) state.
The Clock pin provides 75 MHz clock for the internal
control logic.
Refer to SEN S11054: LSISASx12 Design Considerations
(DB05-000116-xx) for information concerning this signal.
The General Purpose Input/Output (GPIO) pins provide
general purpose inputs and/or outputs.
The UART Output pin provides the UART output from the
serial debugger.
Section 3.7, “Multiplexed SIO Interface,”
for the

Related parts for LSISASX12