LSISASX12 LSI, LSISASX12 Datasheet - Page 265

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

SIO Adapter Control
SIO Control Select bit
SIO Pattern Definition 0
SIO Pattern Definition 1
SIO Pattern Definition 2
SIO Pattern Definition 3
SIO_CFG register
SioClkin 2-7,
SioClkout
SioDin 2-7,
SioDout 2-7,
SioEnd 2-7,
Siolkout
SioStart 2-7,
slash
slave addressing 2-30,
slave read
slave write operation
SMP 1-2, 1-5, 1-6,
SMP command
SMP commands
SMP target 1-2, 2-23,
SMP target register map
SmpPhyOp
SPhynx
SPhynx link registers
SPhynx phy registers
spin mode 2-8,
spin number 2-8,
spin up 1-6,
spin-up
spin-up control
spin-up delay
SSP 1-2, 1-5,
status LED 2-6,
STP 1-2, 1-5, 1-6, 2-3,
STP doorbell
STP interface
output data control
receive
target
vendor-specific commands
WWN
commands
data transfer rates
doorbell
features
initiator address
3-1
1-6
2-4
2-7
2-4
4-7
3-8
4-57
2-33
2-30
1-7
3-7
4-118
3-7
2-8
3-7
3-7
3-8
2-30
4-14
2-28
1-6
4-118
2-20
4-14
4-94
3-6
2-12
4-14
3-8
2-3
4-87
4-71
2-32
4-75
4-93
1-7
Index
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
4-59
4-15
2-26
2-31
2-30
4-67
4-67
4-68
4-69
4-72
2-12
STP target 2-5, 2-28,
STP target register map
STP-SEP
STP-SEP doorbell 2-30,
stress ratings
subtractive decode enable
subtractive routing
supply current
supply voltage
synchronization
T
Ta
table routing
target enclosure management bridge
TCK
TCK,
TDI 3-8,
TDiode_N
TDiode_P
TDO 3-8,
temperature
test signals
thermal diode
thermal resistance
timers
timing
Tj
TMS 3-8,
TN
TN/
top-level address map
transfer length
transmit mux
transmit scramble override
transmitted count
TRST/ 3-8,
TX
5-2
SAS address
junction
operating free air
storage
signals
spin up
PCI and PCI-X
reset
polarity
5-2
1-6
5-5
3-8
3-8
5-6
test
5-7
5-6
5-4
5-6
2-30
3-8
3-9
3-9
4-15
2-9
5-2
5-2
5-6
2-10
4-55
5-2
3-9
5-2
5-2
4-138
3-7
4-108
4-120
5-7
2-10
5-2
5-2
4-15
4-2
4-99
4-134
4-128
4-113
1-5
IX-7