LSISASX12 LSI, LSISASX12 Datasheet - Page 33
LSISASX12
Manufacturer Part Number
LSISASX12
Description
Manufacturer
LSI
Datasheet
1.LSISASX12.pdf
(268 pages)
Specifications of LSISASX12
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2.3
2.3.1
2.3.2
Addressing
Address Spaces
SAS Addressing
The LSISASx12 employs hardware logic to compare requested path
attributes with all valid entries in each selected bank. If a match is found,
the LSISASx12 attempts to form a link between the devices.
This section discusses the different address spaces for the LSISASx12
and SAS addressing.
The LSISASx12 internal registers are divided into the primary internal
register space and the EMB register space. The primary internal
registers allow access to most registers in the device, including registers
for the configuration manager, the connection manager, and the
individual SPhynx modules. The primary internal registers may be
accessed through the serial debugger, the SMP target, the EMB, or the
serial EEPROM boot loader. The primary internal registers are described
in
through
page
The EMB registers have their own register space, which the primary
internal registers cannot access. However, the EMB can access the
primary internal registers through its register space. Through the EMB,
the SEP can access the primary internal registers for device
configuration and/or LED control. Access to these registers is
accomplished by placing the desired command and address into the
RR_Command0 - RR_Command3
data to be written is placed in the
read operations data returned from the primary internal registers is
placed into the
RR_Control
internal registers. These registers are described in
Slave Registers,” on page
Each LSISASx12 expander requires a block of 16 addresses starting at
0x000–0xFFFF. When performing STP-SATA Bridge addressing or
Addressing
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Section 4.1, “Primary Internal Registers Address Map,” on page 4-2
4-124.
Section 4.6, “Expander Connection Manager Registers,” on
register causes execution of the command to the primary
RR_Data0 - RR_Data7
4-133.
RR_Data0 - RR_Data7
registers. For write operations the
registers. Writing to the
Section 4.7, “EMB
registers. For
2-11
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