LSISASX12 LSI, LSISASX12 Datasheet - Page 218

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x506
Read/Write
4-140
7
0
0
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
0
Error Detection Control
0
Reserved
Payload CRC Error
When CRC checking is enabled, the LSISASx12 sets this
bit when it detects a CRC error in the payload bytes of a
write transfer. The LSISASx12 asserts an interrupt to the
SEP to alert the SEP of the CRC error condition. Write a
1 to this bit to clear it.
The Transfer Type bits of the
cate the type of I
contain the CRC error. The
CRC
and the CRC value that was expected.
Header CRC Error
When CRC checking is enabled, the LSISASx12 sets this
bit when it detects a CRC error in the header bytes of a
write or read transfer. The LSISASx12 asserts an inter-
rupt to the SEP to alert the SEP of the CRC error condi-
tion. Write a 1 to this bit to clear it.
The Transfer Type bits of the
cate the type of I
contain the CRC error. The
CRC
and the CRC value that was expected.
Enable CRC
Setting this bit enables CRC error detection for I
fers. Clearing this bit disables error detection. Error
detection is enabled after a reset.
0
registers indicate the actual CRC that was received
registers indicate the actual CRC that was received
0
2
2
C write transaction (byte or block) that
C write transaction (byte or block) that
0
Actual CRC
Actual CRC
Error Status
Error Status
0
1
and
and
register indi-
register indi-
Expected
Expected
2
C trans-
[7:3]
2
1
0