LSISASX12 LSI, LSISASX12 Datasheet - Page 50

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

2.7
2-28
STP Enclosure Management Interface
Example 2 – This example uses the
create a repeating pattern of 1500 ms OFF and 500 ms ON.
This section describes the STP interface. This block contains the I
clock, data, and interrupt signals. The enclosure management bridge
(EMB) provides data integrity checking on the I
The STP Target consists of:
The STP Target is responsible for the following tasks:
Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
–
–
–
–
STP Link Layer
STP Port Layer
STP Transport Layer
STP Application Layer
Accepting STP OAFs.
Rejecting OAFs when the
–
–
–
–
Managing STP Affiliations.
Receiving SATA Frame Information Structures (FIS).
Checking CRC on inbound SATA FIS.
Program the Pattern Definition 0 register to
0b00000111110000011111.
Set the SIO Control Select bit in the
to 0b1 to enable the enhanced SGPIO interface.
Set the Timebase bit to 0b1 to program a time base of 100 ms.
Program Pattern Definition 3 to 0b11111000000000000000.
OAF protocol is not STP
OAF initiator bit is cleared to 0b0
OAF Features bits [3:0] are not cleared to 0b0000
STP Target has an existing Initiator Affiliation, but not with the
requesting STP Initiator.
SIO Pattern Definition 3
SIO Adapter Control
2
C bus.
register
register
2
C