LSISASX12 LSI, LSISASX12 Datasheet - Page 172

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x0010
Read/Write
4-94
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4.7
Table 4.8
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
0x08–0xFF
Phy Op
0x2C–0x30
0x38–0xFF
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Offset
0x28
0x34
SAS Phy Register Map (Cont.)
Phy Operations Encodings
Reserved
PhySMPOp
Writing to this field initiates commands as outlined in
Table
respective command completes. If the current command
does not complete before writing a new command to this
field, then the old command aborts and the new com-
mand initiates.
Power down the GigaBlaze transceivers and reset the phy.
Perform a phy reset sequence and send a HARD_RESET
SMP Command
4.8. The LSISASx12 clears this bit field when the
16 15
Perform a phy reset sequence.
Send port selector sequence
Clear all error log registers.
Clear active affiliation.
No Operation.
Register Name
Operation
Reserved.
Reserved.
Test Register
Custom Jitter
primitive.
Reserved
Reserved
8 7
0
0 0 0 0
[31:8]
0
[7:0]
0
0