LSISASX12 LSI, LSISASX12 Datasheet - Page 104

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4058
Read/Write
4-26
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register determines the number of bytes transferred during receive
transfers. The API2C core ignores writes to this register during the
execution of a data transfer command.
R
RXTL
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
API2C Receive Transfer Length
Reserved
These bits are reserved.
Receive Transfer Length
This field determines the number of bytes received during
API2C read transfers.
The API2C receives this number of data bytes from a
slave (the Serial EEPROM) and writes them to the
Receive FIFO. When the transfer length is reached, the
master state machine either issues a Stop command, or
holds the SCL signal LOW and awaits another command.
If the Receive FIFO becomes full before the receive
transfer length is reached, the master state machine
inserts wait cycles by holding the SCL signal LOW.
A value of 0 for this field is illegal for the Automatic Trans-
fer (receive) and Sequence Transfer commands. If this
field is set to 0 when these commands are issued, the
API2C core reports an error in the
rupt Status
For a manual command, a value of 0 causes the master
state machine to send only the address phase informa-
tion, and then to hold the SCL signal LOW while awaiting
another command.
16 15
register.
8 7
API2C Master Inter-
0
0 0 0 0
[31:8]
0
[7:0]
0
0