LSISASX12 LSI, LSISASX12 Datasheet - Page 229

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

5.2
Table 5.19
5.3
Symbol Parameter
t
t
1
2
AC Characteristics
Pinout
Reset pulse width
Reset deasserted setup to CLK HIGH
Reset Input
The AC characteristics described in this section apply over the entire
range of operating conditions (refer to
Chip timing is based on simulation at worst case voltage, temperature,
and processing. Timing was developed with a load capacitance of 50 pF.
The LSISASx12 requires a 75MHz input clock having an accuracy of at
least 50ppm on both the REFCLK and CLK pins. The duty cycle
required is 40-60% worst case. Refer to SEN S11054: LSISASx12
Design Considerations (Document Number: DB05-000116-xx) for
information concerning using a single oscillator to drive both input clocks.
Table 5.19
Figure 5.1
Table 5.20
the signal listing by BGA position.
AC Characteristics
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
RST/
CLK
provides the signal listing by signal name.
and
Reset Input
Figure 5.1
t
1
provide reset input timing data.
Figure 5.2
Section 5.1, “DC
t
2
provides a BGA diagram.
Min
10
Table 5.21
0
Characteristics.”)
Max
–
–
provides
Units
ns
ns
5-7