LSISASX12 LSI, LSISASX12 Datasheet - Page 71

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

3.4
Table 3.2
3.5
Table 3.3
Signal Name
BSL_SCL
BSL_SD
Signal Name
EMB_SCL
EMB_SD
EMB_DB_INT
EMB_CRC_INT
ISTWI_ADDR[1:0]
Serial EEPROM Signals
I
2
C and EMB Signals
Serial EEPROM Interface Signal Description
I
2
C and EMB Signal Description
Table 3.2
Table 3.3
Serial EEPROM Signals
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
BGA Position I/O
AE3
AD4
BGA Position I/O
AE4
AF3
AF4
AD5
AA8, AE5
describes the serial EEPROM bus signals.
describes the I
I/O
I/O
I/O
I/O
O
O
I
Description
The Serial EEPROM Interface Clock signal provides the
clock signal for the serial EEPROM.
The Serial EEPROM Interface Data signal provides the
data signal for the serial EEPROM.
Description
The EMB Clock pin provides the clock signal for the I
bus.
The EMB Data pin provides the data signal for the I
bus.
The Enclosure Management Doorbell Interrupt pin
provides the active HIGH doorbell interrupt from the
enclosure management bridge to the external enclosure
services processor.
The Enclosure Management CRC Error Interrupt pin
provides the active HIGH CRC error interrupt from the
enclosure management bridge to the external enclosure
services processor.
The I
This bus serves the following functions:
Provides the lower two bits of the address to which the
enclosure management bridge responds. The
additional address bits are hard-coded. This structure
enables a single enclosure services processor to
address multiple expanders.
Provides the block offset of the configuration data in
the serial EEPROM memory to the boot strap loader.
This structure enables a single serial EEPROM to
contain separate configuration data for up to four
LSISASx12 expanders.
2
2
C and EMB signals.
C Addresses
2
C
2
3-5
C