LSISASX12 LSI, LSISASX12 Datasheet - Page 146

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0xC048
Read/Write
4-68
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register controls the enhanced SGPIO pattern definition on the
LSISASx12A expander. This register is not present on the LSISASx12
expander.
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
shift. Setting this bit causes the pattern to rotate at 10 Hz,
which provides an interval of 100 ms between each bit
shift.
Reserved
Pattern 1
This field contains pattern 1. This pattern is sampled at
bit 0.
Timebase 2
Clearing this bit causes the pattern to rotate at 40 Hz,
which provides an interval of 25 ms between each bit
shift. Setting this bit causes the pattern to rotate at 10 Hz,
which provides an interval of 100 ms between each bit
shift.
Reserved
Pattern 2
This field contains pattern 2. This pattern is sampled at
bit 0.
SIO Pattern Definition 2
16 15
8 7
0
0 0 0 0
[30:20]
[30:20]
[19:0]
[19:0]
0
31
0
0