HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 102

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
A direct coupling of two PCM time slots uses a PCM switching buffer. This connection requires
a HFC-channel number (resp. the same FIFO number). An arbitrary HFC-channel number can be
chosen. If there are less than 31 transmit and receive FIFOs it is usefull to chose a HFC-channel
number that is greater than the maximum FIFO number generally. This saves FIFO resources where
no data is stored in a FIFO.
Subchannel processing
If the data stream of a FIFO does not require full 8 kByte/s data rate, the subchannel processor might
be used. Unused bits can be masked out with an arbitrary mask byte.
For D- and E-channel processing the subchannel functionality must be enabled. Only two bits of a
data byte are processed every 125 s.
In transparent mode only the non-masked bits of a byte are transmitted. Masked bits are taken from
the register A_CH_MSK. So the effective FIFO data rate always remains 8 kByte/s whereas the
usable data rate depends on the number of non-masked bits.
In HDLC mode the data rate of the FIFO is reduced according to how many bits are not masked out.
Please see Section 3.5 on page 113 for details concerning the subchannel processor.
Example for SM
Figure 3.5 shows an example with three bidirectional connections (FIFO-to-S/T, FIFO-to-PCM and
PCM-to-S/T). The FIFO box on the left side contains number and direction of the used FIFOs. The
S/T and PCM boxes on the right side contain the S/T-channels and PCM time slot numbers and
directions which are used in this example. Black lines illustrate data paths, whereas dotted lines
symbolize blocked resources. These are not used for data transmission, but they are necessary to
enable the settings.
The following settings demonstrate the required register values to establish the connection. All
involved FIFOs have to be enabled with V_HDLC_TRP
A_CON_HDLC[FIFO]. The non-specified bitmap values depend on the desired FIFO configuration.
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➊
FIFO-to-S/T
As HFC-channel and FIFO numbers are the same, a selected S/T-channel specifies the corre-
sponding FIFO (and same in inverse, of course). There is no need of programming this assigner.
G
All settings in Figure 3.5 are configured in bidirectional data paths due to typical
applications of the HFC-4S / 8S. However, transmit and receive directions are
independent from each other and could occur one at a time as well.
Please note !
R_FIFO
A_CON_HDLC[9,TX] : V_DATA_FLOW
R_FIFO
A_CON_HDLC[9,RX] : V_DATA_FLOW
: V_FIFO_DIR
: V_FIFO_NUM
: V_FIFO_DIR
: V_FIFO_NUM
Data Sheet
Data flow
0
’100’
9
1
’100’
9
·
V_TRP_IRQ
FIFO
(transmit FIFO)
(FIFO #9)
FIFO
(receive FIFO)
(FIFO #9)
S/T
S/T
March 2003 (rev. A)
¼
in the register
Cologne
Chip