HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 111

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

chosen. To select FIFO[12,TX] as first FIFO R_FIRST_FIFO is set as follows:
March 2003 (rev. A)
HFC-4S
HFC-8S
➊
➋
FIFO-to-S/T
The bidirectional FIFO-to-S/T connection allocates the list indices 0 and 1 as follows:
FIFO-to-PCM
The following two list entries (indices 2 and 3) define the bidirectional FIFO-to-PCM con-
nections. Two S/T-channels are blocked. But S/T-channel resources are saved because HFC-
channels that are assigned to not used E-channels are selected.
R_FIRST_FIFO : V_FIRST_FIFO_DIR
R_FSM_IDX
A_CON_HDLC[0] : V_DATA_FLOW
A_CHANNEL[0] : V_CH_DIR0
A_FIFO_SEQ[0] : V_NEXT_FIFO_DIR
R_FSM_IDX
A_CON_HDLC[1] : V_DATA_FLOW
A_CHANNEL[1] : V_CH_DIR0
A_FIFO_SEQ[1] : V_NEXT_FIFO_DIR
Table 3.5: List specification of the example in Figure 3.10
List index
: V_FIRST_FIFO_NUM
0
1
2
3
4
5
6
7
: V_IDX
: V_CH_NUM0
: V_NEXT_FIFO_NUM
: V_SEQ_END
: V_IDX
: V_CH_NUM0
: V_NEXT_FIFO_NUM
: V_SEQ_END
FIFO[12,TX]
FIFO[12,RX]
FIFO[13,RX]
FIFO[13,TX]
FIFO[14,TX]
FIFO[14,RX]
FIFO[14,TX]
FIFO[14,RX]
Data Sheet
Data flow
Connection
0
12
S/T interf. #3, B1 TX
S/T interf. #3, B1 RX
PCM slot[21,RX]
PCM slot[21,TX]
S/T interf. #4, B2 TX
S/T interf. #4, B2 RX
S/T interf. #5, B1 TX
S/T interf. #5, B1 RX
’100’
0
1
’100’
1
1
0
12
12
0
1
12
13
0
(transmit FIFO)
(FIFO #12)
(FIFO
(next: receive FIFO)
(FIFO
(next: receive FIFO)
(list index 0, FIFO[12,TX])
(transmit HFC-channel)
(HFC-channel #12)
(next: FIFO #12)
(continue)
(list index 1, FIFO[12,RX])
(receive HFC-channel)
(HFC-channel #12)
(next: FIFO #13)
(continue)
S/T)
S/T)
Cologne
Chip
111 of 273