HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 220

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
The timings are defined by writing the number of idle clock cycles for an access to
the bitmaps V_BRG_TIM0_IDLE . . . V_BRG_TIM3_IDLE of the registers R_BRG_TIM0
. . . R_BRG_TIM3.
V_BRG_TIM0_CLK . . . V_BRG_TIM3_CLK of the same registers.
The timing can be configured for each chip select and read / write operation independently by pro-
gramming the registers R_BRG_TIM_SEL01 . . . R_BRG_TIM_SEL67.
220 of 273
Host
R_BRG_CTRL
V_BRG_CS
V_BRG_ADDR
V_BRG_CS_SRC
register and address bytes
0..2
3..4
10
11
7
0
1
2
3
4
5
6
7
8
9
Figure 11.3: Host bridge structure in memory mapped mode
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7],CS[0]
A[8],CS[1]
A[9],CS[2]
M[0]
M[1]
CS[0..2]
A[10,11]
The number of active clock cycles are defined in the bitmaps
Auxiliary interface
HFC-4S / HFC 8S
Data Sheet
0
1
3
12
/BRG_CS[0..7]
CS[0..2]
Demultiplexer
BRG_A[0..11]
BRG_D[0..7]
Access
mode
/BRG_WR
/BRG_RD
-
0
7
connected pins
8
2
up to
12
8
2
March 2003 (rev. A)
address
data
control
chip select
address
data
control
chip select
address
data
control
chip select
Cologne
Chip
device #0
device #1
device #7
external
external
external