HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 224

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HFC-4S

Manufacturer Part Number
HFC-4S
Description
Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
Manufacturer
Cologne Chip AG
Datasheet
HFC-4S
HFC-8S
224 of 273
R_BRG_TIM0
Auxiliary bridge timing configuration register for timing 0
3..0
7..4
R_BRG_TIM1
Auxiliary bridge timing configuration register for timing 1
3..0
7..4
R_BRG_TIM2
Auxiliary bridge timing configuration register for timing 2
3..0
7..4
Bits
Bits
Bits
0
0
0
0
0
0
Value
Value
Value
Reset
Reset
Reset
Name
V_BRG_TIM0_IDLE
V_BRG_TIM0_CLK
Name
V_BRG_TIM1_IDLE
V_BRG_TIM1_CLK
Name
V_BRG_TIM2_IDLE
V_BRG_TIM2_CLK
Auxiliary interface
(write only)
(write only)
(write only)
Data Sheet
Description
Idle cycles
Active cycles
Description
Idle cycles
Active cycles
Description
Idle cycles
Active cycles
Number of idle system clock cycles for read / write
signal
Number of active system clock cycles for
read / write signal
Number of idle clock cycles for read / write signal
Number of active clock cycles for read / write signal
Number of idle clock cycles for read / write signal
Number of active clock cycles for read / write signal
March 2003 (rev. A)
Cologne
Chip
0x4A
0x48
0x49

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