HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 230

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
12.1 Clock
The clock generation circuitry of the HFC-4S / 8S is shown in Figure 12.1. Two different crystal
frequencies can be used. Pin CLK_MODE must be set as shown in Table 12.3 to ensure a system
clock of 24,576 MHz.
ISDN applications need exactly 24,576 MHz. It is recommended to ensure an accuracy of ¦ 50 ppm.
12.2 Reset
HFC-4S / 8S has a level sensitive RESET input. This is low active in PCI mode (pin name RST#) and
high active in all other modes (pin name RESET). The MODE0 / MODE1 pins must be valid during
RESET and /SPISEL must be ’1’ (inactive). After RESET HFC-4S / 8S enters an initialization
sequence.
The HFC-4S / 8S has 4 different software resets. The FIFO registers, PCM registers and S/T registers
can be reset independently with the bits of the register R_CIRM which are listed in Table12.4. The
reset bits must be cleared by software.
Information about the registers reset by the different resets can be found in the register list on pages16
and 14.
230 of 273
Crystal frequency
Clock, reset, interrupt, timer and watchdog
Figure 12.1: Standard HFC-4S / 8S quartz circuitry
U1
HFC-4S/HFC-8S
24,576 MHz
49,152 MHz
CLK_MODE
OSC_OUT
OSC_IN
Table 12.3: Quartz selection
92
91
90
CLK_MODE
Data Sheet
’1’
’0’
+ 3 . 3 V
G N D
R1
C1
4 7 p
2 4 . 5 7 6 M H z
Q 1
System clock
G N D
24,576 MHz
24,576 MHz
R2
C2
4 7 p
ÄÃÁ
March 2003 (rev. A)
Cologne
Chip