HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 132

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
frame which is just being transmitted to the S/T interface side of the HFC-4S / 8S.
end of frame pointer of the current output frame.
In the transmit HFC-channels
driver wants to say “end of transmit frame”. This is done by setting the bit V_INC_F in register
R_INC_RES_FIFO. Then the current value of
start address of the next frame.
transmit FIFOs if V_FZ_MD in the register R_RAM_MISC is set.
4.3.2 Automatical D-channel frame repetition
The D-channel transmit FIFO has a special feature. If the S/T interface signals a D-channel contention
before the CRC is sent the
HFC-4S / 8S tries to repeat the frame automatically.
4.3.3 FIFO full condition in HDLC transmit HFC-channels
Due to the limited number of registers in the HFC-4S / 8S the driver software must maintain a list of
frame start and end addresses to calculate the actual FIFO size and to check the FIFO full condition.
Because there is a maximum of 32 (resp. 16 with 32k RAM) frame counter values and the start address
of a frame is the incremented value of the end address of the last frame the memory table needs to
have only 32 (resp. 16) values of 16 bit instead of 64 (resp. 32).
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CRC2
G
The HFC-4S / 8S begins to transmit the bytes from a FIFO at the moment the
FIFO is changed (writing R_FIFO) or the
to the FIFO that is already selected also starts the transmission. Thus by selecting
the same FIFO again transmission can be started.
HDLC flag
01111110
Please note !
data
data
Figure 4.2: FIFO data organization in HDLC mode
FIFO handling and HDLC controller
¾
zero - inserted data
counter is set to the starting address of the current frame and the
½
is only incremented from the host interface side if the software
¾´ ¾µ
can not be accessed while
Data Sheet
frame
Z1 (F1)
½
data
data
is stored,
½
counter is incremented. Switching
CRC1
CRC1
½
is incremented and
CRC2
CRC2
½´ ¾µ
March 2003 (rev. A)
HDLC-frame
Data in
transmit FIFO
Data in
receive FIFO
STAT = 00h if CRC o.k.
can be accessed for
HDLC flag
01111110
STAT
½´ ¾µ
Cologne
Chip
1 is used as
is the