HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 120

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
120 of 273
R_FIFO
FIFO selection register
This multi-register is selected with bitmap V_FSM_MD = 0 of the register R_FIFO_MD. It is
only used in SM and CSM.
0
5..1
6
7
R_FSM_IDX
Index register of the FIFO sequence
This multi-register is selected with bitmap V_FSM_MD = 1 of the register R_FIFO_MD. It is
only used in FSM.
5..0
7..6
Bits
Bits
0x00
0
0
0
Value
Value
Reset
Reset
Name
V_FIFO_DIR
V_FIFO_NUM
(reserved)
V_REV
Name
V_IDX
(reserved)
(write only)
(write only)
Data Sheet
Data flow
Description
FIFO data direction
FIFO number
Description
List index
’0’ = transmit FIFO data
’1’ = receive FIFO data
Must be ’0’.
Bit order
’0’ = normal bit order
’1’ = reversed bit order
Normal bit order means LSB first in HDLC mode
and MSB first in transparent mode. The bit order is
being reversed for the data stored into the FIFO or
when the data is read from the FIFO.
The list index must be in the range 0 . . . 63.
Must be ’00’.
March 2003 (rev. A)
Cologne
Chip
0x0F
0x0F