HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 163

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-4S
HFC-8S
A_ST_CTRL0 [ST]
Control register of the selected S/T interface, register 0
Before writing this array register the S/T interface must be selected by register R_ST_SEL.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Value
Reset
V_B1_EN
V_B2_EN
V_ST_MD
V_D_PRIO
V_SQ_EN
V_96KHZ
V_TX_LI
V_ST_STOP
Name
S/T interface
(write only)
Data Sheet
Description
B1-channel transmit
’0’ = B1 send data disabled (permanent ’1’s sent in
activated states)
’1’ = B1 send data enabled
B2-channel transmit
’0’ = B2 send data disabled (permanent ’1’s sent in
activated states)
’1’ = B2 send data enabled
S/T interface mode
’0’ = TE mode
’1’ = NT mode
D-channel priority
’0’ = high priority 8/9
’1’ = low priority 10/11
S/Q bits transmission
’0’ = S/Q bits disabled
’1’ = S/Q bits and multiframe enabled
96 kHz test signal
’0’ = normal operation
’1’ = send 96 kHz transmit test signal (alternating
zeros)
Transmitter line setup
This bit must be configured depending on the used
S/T module and circuitry to match the 400 ª pulse
mask test.
’0’ = capacitive line mode
’1’ = non capacitive line mode
Power down
’0’ = external receiver activated
’1’ = power down, external receiver disabled
Cologne
Chip
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