HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 236

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HFC-4S

Manufacturer Part Number
HFC-4S
Description
Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
Manufacturer
Cologne Chip AG
Datasheet
HFC-4S
HFC-8S
236 of 273
R_IRQ_MISC
Miscellaneous interrupt status register
All bits of this register are cleared after a read access.
0
1
2
3
7..4
Bits
0
0
0
Value
Reset
Name
(reserved)
V_TI_IRQ
V_IRQ_PROC
V_DTMF_IRQ
(reserved)
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Description
Timer interrupt
DTMF detection interrupt
Must be ’0’.
’1’ = timer elapsed
Processing / non processing transition interrupt
status
’1’ = The HFC-4S / 8S has changed from
processing to non processing phase (every 125 s).
’1’ = DTMF detection has been finished. The
results can be read from the RAM.
Must be ’0000’.
March 2003 (rev. A)
Cologne
Chip
0x11

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