HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 75

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

2.5.2.4 16 bit processors in mode 4 (Intel, multiplexed)
16 bit processors can either read data with byte or word access. Only 8 bit are used for address
decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A word read is shown in Figure 2.15. FIFO and
alternatively. The 16 bit processor must support byte access because all other register read accesses
must have a width of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 switch the data bus D15 . . . D0 from tristate into
data driven state (see Table 2.22 on page 77).
In mode 4 (Intel, multiplexed) the states
must be fulfilled to drive data out. The data bus is stable after
Ø
Address and /BE require a setup time
lines is
is not required.
An 8 bit read access (low byte) is performed in the same way as it is done with 8 bit processors. Thus
see Figure 2.13 for the timing specification.
March 2003 (rev. A)
HFC-4S
HFC-8S
AD[31:16]
/RD+/CS
AD[15:8]
/BE[3:2]
/BE[1:0]
AD[7:0]
/WR
ALE
À
.
Ø
À
. If two consecutive read accesses are on the same address, multiple register address write
Figure 2.15: Word read access from 16 bit processors in mode 4 (Intel, multiplexed)
t
address
ALE
byte enable
t
/BE
AS
address
t
AH
’0’
t
ALEH
and
Universal external bus interface
Ø
´
/RD
Ë
which starts with the
Data Sheet
t
word read access
RDmin
·
t
t
DRDZ
permanently high
permanently high
RD
/CS
- / -counter read access have 8 bit or 16 bit width
µ
data
data
’0’
t
DRDH
and
Ø
Ñ Ò
t
of ALE. The hold time of these
CYCLE
/WR
and returns into tristate after
word read access
t
RDmin
t
’1’
t
DRDZ
RD
data
data
Cologne
Chip
t
DRDH
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