HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 219

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

11.2.4 Host mode
Auxiliary-to-host accesses can be performed in two ways. In I/O mapped mode two CIP bytes must
be programmed to execute read and write accesses. The second way uses the memory mapped mode
and the register R_BRG_CTRL.
Bridge access in I/O mapped mode
This mode is supported for PCI I/O mode, PCMCIA, ISA PnP and SPI modes.
The host-to-auxiliary bridge uses two CIP bytes for read and write access control in I/O mapped mode.
Figure 11.2 shows the bit mapping of these bytes. Please see Figure 11.2 on page 218 concerning the
CIP bytes. If V_BRG_EN is set in the register R_BRG_PCM_CFG all CIP writes must be 16 bit
writes.
As A[11] and CS[0] are located on the same CIP bit, it is either possible to use more than 4 external
devices with 11 bit address bus width or to use up to 4 external devices with full 12 bit address bus
width.
With 12 bit address space a small external circuitry is required to connect the external devices to the
HFC-4S / 8S chip select lines. In detail, /BRG_CS0 and /BRG_CS1 must be OR-ed to select the
first device, /BRG_CS2 and /BRG_CS3 must be OR-ed to select the second device, and so on.
Bridge access in memory mapped mode
This mode is supported for PCI memory mapped mode and processor mode.
In memory mapped mode the control register R_BRG_CTRL can be used to perfom read and write
accesses with a large address space. External devices with up to 10 address lines do not require this
register. If R_BRG_CTRL is not used, the exact number of available address lines depends on the
number of external devices. An overview of this functionality is given in Figure11.3.
V_BRG_CS_SRC of the register R_BRG_CTRL selects the source of the chip select signals. By
default the address lines 7 . . . 9 are taken.
11.3 Timing definitions
The timing requirements of the connected external devices can be fulfilled by programming different
timing configurations. Four different read and write timings can be programmed in the registers
R_BRG_TIM0 . . . R_BRG_TIM3.
March 2003 (rev. A)
HFC-4S
HFC-8S
1. If the external devices have not more than 7 address lines, the register R_BRG_CTRL is not
2. External devices with 8 . . . 10 address lines take one, two or even all chip select lines CS[0..2]
3. The full 12 bit address space can be used with the bitmap V_BRG_ADDR of the register
necessary for bridge accesses. The bridge operation can be performed with 12 address bits as
shown in Figure 11.3. Up to 8 external devices can be connected to the HFC-4S / 8S.
from the address specification bits. The number of chip select output signals on the pins
/BRG_CS0 . . . /BRG_CS7 is reduced appropriately. If A[7] . . . A[9] are used in parallel
to chip select signals, the bit V_BRG_CS_SRC must be set in the register R_BRG_CTRL.
R_BRG_CTRL. The address bits A[10] and A[11] have to be specified there.
Auxiliary interface
Data Sheet
Cologne
Chip
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