HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 69
![no-image](/images/no-image-200.jpg)
HFC-4S
Manufacturer Part Number
HFC-4S
Description
Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
Manufacturer
Cologne Chip AG
Datasheet
1.HFC-4S.pdf
(273 pages)
- Current page: 69 of 273
- Download datasheet (3Mb)
2.5.2.2 16 bit processors in mode 2 (Motorola) and mode 3 (Intel)
16 bit processors can either read data with byte or word access like shown in Figure2.11. FIFO and
byte access because all other register read accesses must have a width of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 switch the data bus D15 . . . D0 from tristate into
data driven state (see Table 2.19).
Data can be read in mode 2 (Motorola) with
In mode 3 (Intel, non-multiplexed) the states
March 2003 (rev. A)
HFC-4S
HFC-8S
/DS+/CS
/RD+/CS
/BE[3:2]
D[15:8]
- / -counter read access have 8 bit or 16 bit width alternatively. The 16 bit processor must support
A[7:0]
D[7:0]
Figure 2.11: Byte and word read access from 16 bit processors in mode 2 (Motorola) and mode 3 (Intel)
/BE1
/BE0
R/W
/WR
in mode2 only
(Motorola:)
in mode 3 only
(Intel):
word read access
t
/BE
AS
/BE
byte enable
byte enable
t
RWS
address
t
t
DRDZ
DRDZ
t
’0’
RD
’0’
t
RDmin
data
data
and
t
and
Universal external bus interface
t
t
t
AH
DRDH
DRDH
RWH
´
´
/DS
/RD
t
CYCLE
Data Sheet
·
low byte read access
·
permanently high
permanently high
t
/CS
AS
/CS
µ
byte enable
byte enable
t
RWS
µ
address
t
DRDZ
t
RD
’0’
’0’
t
RDmin
data
and
t
t
t
AH
and
DRDH
RWH
R/W
/WR
t
CYCLE
high byte read access
t
AS
’1’
’1’
byte enable
byte enable
t
RWS
address
t
DRDZ
t
RD
t
RDmin
data
Cologne
Chip
t
69 of 273
t
AH
RWH
t
DRDH
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