HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 65

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HFC-4S

Manufacturer Part Number
HFC-4S
Description
Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
Manufacturer
Cologne Chip AG
Datasheet
March 2003 (rev. A)
HFC-4S
HFC-8S
Table 2.17: Overview of read and write accesses in processor interface mode (X
G
/BE2 and /BE3 must always be ’1’ in mode 2 and mode 3.
Mode
2 & 3
2 & 3
2 & 3
2 & 3
4
4
4
4
4
4
Important !
/CS
X
1
0
0
0
0
0
0
Processor
Table 2.18: Timing diagrams of the parallel processor interface
(/DS, /RD)
16 bit
16 bit
16 bit
16 bit
32 bit
32 bit
8 bit
8 bit
8 bit
8 bit
/IOR
X
1
0
0
0
1
0
1
16 bit & 8 bit
16 bit & 8 bit
Access type
Universal external bus interface
( : 1-pulse latches register address)
(R/W, /WR)
16 bit
16 bit
32 bit
32 bit
/IOW
8 bit
8 bit
8 bit
8 bit
X
1
0
1
0
1
0
1
Data Sheet
read
write
read
write
read
write
read
write
read
write
ALE
0
0
X
X
1
1
0
0
Figure
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.9
Operation
no access
no access
read data
write data
read data
write data
read data
write data
Timing
on page
66
68
69
71
73
74
75
76
77
79
interface mode
Processor
2.20
2.21
2.20
2.21
2.23
2.24
2.23
2.24
2.23
2.24
mode 2
mode 2
mode 3
mode 3
mode 4
mode 4
Timing values
table
all
all
on page
don’t care)
70
72
70
72
78
80
78
80
78
80
Cologne
Chip
65 of 273

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