HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 67

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

Address and /BE0 (if not fixed to low) require a setup time
byte enable signals are valid. The hold time of these lines is
March 2003 (rev. A)
HFC-4S
HFC-8S
G
In some applications it may be difficult to implement a long read access (
For this reason there is an alternative method with two register read accesses with
Ø
The
the
R_IRQ_FIFO_BL0 . . . R_IRQ_FIFO_BL7 and R_RAM_DATA.
¡
Ø
1. The read access to the target register initiates a data transmission from the
2. . . . but the data byte is already internally buffered and can be read from
Short read method
ÄÃÁ
RAM to the target register. This job is always done correctly with long and
short
register. Thus the data which is read with a short
the register R_INT_DATA. This second register read access can also be
executed with a short
second one
address
short
¾¼ Ò×
) for only some registers (here called target register).
Ø
each:
read
, but after a short
range
Ø
method
Universal external bus interface
Ä
0xC0
must be met, of course.
Ø
is
Data Sheet
Ø
¾¼ Ò×
. . . 0xFF,
practical
the data is not yet ‘arrived’ at the target
. For the time from the first access to the
these
for
Ø
Ø
À
Ë
.
all
Ø
which starts when all address and
target
must be ignored . . .
read
registers
registers
Ø
are
Cologne
Chip
in
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