HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 272

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
LD
LEN
LEV
LI
LO
LOOP
LOST
LPRIO
MD
MF
MISC
MIX
MSK
MULT
NEG
NEXT
NOINC
NOISE
NUM
OFF
OFLOW
OUT
OVIEW
PAT
PCM
PCMRES
PLL
PNP
POL
PRIO
PROC
PWM
272 of 273
load
length
level
line
low
loop
frame data lost
low priority
mode
multiframe
miscellaneous
mixed
mask
multiple
negative
next
no increment
noise
number
off
overflow
output
overview
pattern
PCM
PCM reset
phase locked loop
plug and play
polarity
priority
processing
pulse width
modulation
RAM
RD
RDY
RES
RESTART
REV
RLD
ROUT
RV
RX
SA6
SCI
SEL
SEQ
SET
SH
SH0H
SH0L
SH1H
SH1L
SL
SLOT
SLOW
SMPL
SPEED
SQ
SRAM
SRC
SRES
ST
STA
STACHG
START
Data Sheet
RAM
read
ready
reset
restart
reverse
reload
routing (of PCM
buffer)
revision
receive
spare bit Ë
state change
interrupt
select
sequence
set
shape
shape 0, high byte
shape 0, low byte
shape 1, high byte
shape 1, low byte
time slot
PCM time slot
slow
sample
S/Q bits
SRAM
source
S/T interface
state, status
state change
start
speed
soft reset
STATUS
STOP
STRES
SUBCH
SUPPR
SWAP
SYNC
SZ
TI
TIM
TIME
TRANS
TRIS
TRP
TS
TX
ULAW
use
WD
WR
WRDLY
Z1
Z12
Z1H
Z1L
Z2
Z2H
Z2L
March 2003 (rev. A)
status
stop
ST reset
subchannel
suppression
(threshold)
swap
synchronize
size
timer
timing
time
transition
tristate
transparent
timestep
transmit
usage
watchdog timer
write
write delay
Z1-counter
Z1- and Z2-counter
Z1-counter, high
byte
Z1-counter, low
byte
Z2-counter
Z2-counter, high
byte
Z2-counter, low
byte
-law
Cologne
Chip