HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 239

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-4S
HFC-8S
R_IRQ_FIFO_BL1
FIFO interrupt register for FIFO block 1
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is
’0’, no interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Value
Reset
V_IRQ_FIFO4_TX
V_IRQ_FIFO4_RX
V_IRQ_FIFO5_TX
V_IRQ_FIFO5_RX
V_IRQ_FIFO6_TX
V_IRQ_FIFO6_RX
V_IRQ_FIFO7_TX
V_IRQ_FIFO7_RX
Name
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Description
Interrupt occured in transmit FIFO 4
Interrupt occured in receive FIFO 4
Interrupt occured in transmit FIFO 5
Interrupt occured in receive FIFO 5
Interrupt occured in transmit FIFO 6
Interrupt occured in receive FIFO 6
Interrupt occured in transmit FIFO 7
Interrupt occured in receive FIFO 7
Cologne
Chip
239 of 273
0xC9