HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 232

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
12.5 Register description
12.5.1 Write only register
232 of 273
R_IRQMSK_MISC
Miscellaneous interrupt status mask register
’0’ means that the interrupt is not used for generating an interrupt on the interrupt pin
197.
0
1
2
3
7..4
R_IRQ_CTRL
Interrupt control register
0
2..1
3
4
7..5
Bits
Bits
0
0
0
0
0
0
Value
Value
Reset
Reset
Name
(reserved)
V_TI_IRQMSK
V_PROC_IRQMSK
V_DTMF_IRQMSK
(reserved)
Name
V_FIFO_IRQ
(reserved)
V_GLOB_IRQ_EN
V_IRQ_POL
(reserved)
Clock, reset, interrupt, timer and watchdog
(write only)
(write only)
Data Sheet
Description
Description
FIFO interrupt
Global interrupt signal enable (pin 197)
Polarity of interrupt signal
Must be ’0’.
Timer elapsed interrupt mask bit
Processing / nonprocessing transition interrupt
mask bit
(every 125 s)
DTMF detection interrupt mask bit
Must be ’0000’.
’0’ = FIFO interrupts disabled
’1’ = FIFO interrupts enabled
Must be ’00’.
’0’ = disable
’1’ = enable
’0’ = low active signal
’1’ = high active signal
Must be ’000’.
March 2003 (rev. A)
Cologne
Chip
0x11
0x13