HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 237

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-4S
HFC-8S
R_STATUS
HFC-4S / 8S status register
0
1
2
3
4
5
6
7
Bits
0
1
0
0
0
0
0
0
Value
Reset
V_BUSY
V_PROC
V_DTMF_IRQSTA
V_LOST_STA
V_SYNC_IN
V_EXT_IRQSTA
V_MISC_IRQSTA
V_FR_IRQSTA
Name
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Description
BUSY / NOBUSY status
’1’ = the HFC-4S / 8S is BUSY after initialising
Reset FIFO, increment -counter or change FIFO
’0’ = the HFC-4S / 8S is not busy, all accesses are
allowed
Processing / non processing status
’1’ = the HFC-4S / 8S is in processing phase (every
125 s)
’0’ = the HFC-4S / 8S is not in processing phase
DTMF interrupt
DTMF interrupt has occured
LOST error (frames have been lost)
This means the HFC-4S / 8S did not process all
data in 125 s. So data may be corrupted.
Bit V_RES_LOST of the R_INC_RES_FIFO
register must be set to reset this bit.
Synchronization input
Value of the SYNC_I input pin
External interrupt
External interrupt has occured
Any miscellaneous interrupt
All enabled miscellaneous interrupts of the register
R_IRQ_MISC are ‘ored’.
Any FIFO interrupt
All enabled FIFO interrupts in the registers
R_IRQ_FIFO_BL0 . . . R_IRQ_FIFO_BL7 are
‘ored’.
Cologne
Chip
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