HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 95

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

FIFO: The FIFOs are buffers between the universal bus interface and the PCM and S/T interfaces.
HFC-channel: HFC-channels are used to define data paths between FIFOs on the one side and PCM
PCM time slot: The PCM data stream is organized in time slots. The number of PCM time slots
Each FIFO, HFC-channel and time slot number exist for transmit and receive direction. The data
rate is always 8 kByte/s for every S/T-channel and every PCM time slot. FIFOs, HFC-channels, S/T-
channels and PCM time slots have always a width of 8 bit.
3.2 Flow controller
The various connections between FIFOs, S/T-channels and PCM time slots are set up by programming
the flow controller, the channel assigner and the PCM slot assigner.
The flow controller sets up connections between FIFOs and the S/T interface, FIFOs and the PCM
interface and between the S/T and PCM interface. The bitmap V_DATA_FLOW of the register
A_CON_HDLC (which exists for each FIFO) configures these connections. The numbering of trans-
mit and corresponding receive FIFOs, HFC-channels and PCM time slots is independent from each
March 2003 (rev. A)
HFC-4S
HFC-8S
1
In this data sheet the shorter expression “slot” instead of “time slot” is also used with the same meaning.
Figure 3.2: Areas of FIFO oriented, HFC-channel oriented and PCM time slot oriented numbering
The HDLC controllers are located on the non host bus side of the FIFOs. The number of
FIFOs depends on the FIFO size configuration (see Section 4.2) and starts with number 0. The
maximum FIFO number is 31. Furthermore data directions transmit and receive are associated
with every FIFO number.
and S/T interfaces on the other side. The HFC-channels are numbered 0 . . . 31. Furthermore
data directions transmit and receive are associated with every HFC-channel number.
It is important not to mix up the HFC-channels of the here discussed data flow (inner circle of
Figure 3.2) with the S/T-channels of the multiple S/T interfaces.
depends on the data rate, i.e. there are 32 time slots (2 MBit/s), 64 time slots (4 MBit/s) or 128
time slots (8 MBit/s). As data directions transmit and receive are associated with every time
slot number, slots are numbered 0 . . . 15, 0 . . . 31 or 0 . . . 63.
interface
host
numbering
PCM slot
oriented
interface
PCM
oriented numbering
numbering
oriented
FIFO
channel
Data Sheet
Data flow
8 or 4 S/T interfaces:
B1-channels
B2-channels
D-channels
E-channels
Cologne
Chip
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