HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 114

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
write this byte for HFC-channel [
first. After this index selection the desired mask byte
The default subchannel configuration of the register A_SUBCH_CFG leads to a transparent behav-
ior. That means, only complete data bytes are transmitted in receive and transmit direction.
3.5.1 Transparent mode
In transparent mode every FIFO has a data rate of 8 kByte/s. Every 125 s one byte of a FIFO is
processed. The subchannel processor takes only the bits that are defined by the FIFO parameters and
inserts them into the channel mask A_CH_MSK.
Received HFC-channel data bytes are stored completely in the FIFO and are independently from the
V_BIT_CNT and V_START_BIT settings.
Simple Mode
As the FIFO and HFC-channel numbers are the same in Simple Mode, only one FIFO can be con-
nected to a HFC-channel. Subchannel processing can do nothing more than mask out some bits of
every transmitted data byte.
Suppose FIFO[
FIFO[
shown in Table 3.6. From every FIFO byte only three bits are transmitted to the HFC-channel. These
bits are accentuated in the table. The other bits are defined by the channel mask.
In receive direction, the subchannel processor has no effect in Simple mode combined with transparent
mode. So received HFC-channel bytes are stored in the FIFO without changing.
Channel Select Mode
In Channel Select Mode it is possible to connect more than one FIFO to a HFC-channel. The config-
uration in Figure 3.11 with three FIFOs can be taken as example. The bit extraction / insertion units
must be configured with the following register settings:
114 of 273
¾
(see Fig. 3.11). Further, the channel mask is defined as A_CH_MSK
Ñ
,TX] data bytes
G
Typically, the R_FIFO register contains always an FIFO index. There is one
exception where the R_FIFO value has a different meaning: The HFC-channel
mask byte is programmed by writing the HFC-channel into the R_FIFO register.
G
The A_CH_MSK array register is indexed by R_FIFO to write the mask byte.
However the mask is assigned to a HFC-channel, namely that HFC-channel
which is assigned to the indexing FIFO.
Important !
Important !
Ñ
,TX] has the register A_SUBCH_CFG settings V_BIT_CNT
Ñ
½
. . .
Ñ
Ò
,TX] the HFC-channel must be written into the R_FIFO register
with bit index
Data Sheet
Data flow
¼
Ñ
can be written with A_CH_MSK =
build up the HFC-channel data bytes as
Å
March 2003 (rev. A)
¿
and V_START_BIT
Å
¼
Cologne
Chip
. Then the
Ñ
.