HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 234

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
234 of 273
A_IRQ_MSK [FIFO]
Interrupt register for the selected FIFO
Before writing this array register the FIFO must be selected by register R_FIFO.
0
1
2
7..3
Bits
0
0
0
Value
Reset
Name
V_IRQ
V_BERT_EN
V_MIX_IRQ
(reserved)
Clock, reset, interrupt, timer and watchdog
(write only)
Data Sheet
Description
Interrupt mask for the selected FIFO
’0’ = disabled
’1’ = enabled
BERT output enable
’0’ = BERT disabled, normal data is transmitted
’1’ = BERT enabled, output of BERT generator is
transmitted
Mixed interrupt generation
’0’ = disabled (normal operation)
’1’ = frame interrupts and transparent interrupts are
both generated in HDLC mode
Must be ’00000’.
March 2003 (rev. A)
Cologne
Chip
0xFF