HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 77

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

2.5.2.5 32 bit processors in mode 4 (Intel, multiplexed)
32 bit processors can either read data with byte, word or double word access. Only 8 bit are used for
address decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A double word read is shown in Figure 2.17. FIFO and
32 bit width alternatively,
processor must support byte access because all other register read accesses must have a width of 8 bit.
/BE3 . . . /BE0 switch the bus lines AD31 . . . AD0 from tristate into data driven state during data
phase (see Table 2.22).
In mode 4 (Intel, multiplexed) the states
March 2003 (rev. A)
HFC-4S
HFC-8S
/RD+/CS
AD[31:8]
/BE[3:0]
AD[7:0]
/WR
ALE
Figure 2.17: Double word read access from 32 bit processors in mode 4 (Intel, multiplexed)
t
address
ALE
byte enable
t
A[0]
AS
address
’X’
’0’
’1’
’0’
’1’
’0’
’0’
’0’
/BE
t
AH
/BE3
’0’
’1’
’1’
’1’
’1’
’0’
’1’
’0’
’0’
-counter read access have 8 bit or 16 bit width alternatively. The 32 bit
t
ALEH
Table 2.22: Data access width in mode 4
and
Universal external bus interface
/BE2
’1’
’1’
’1’
’0’
’1’
’1’
’0’
’0’
´
/BE1
/RD
’1’
’1’
’0’
’1’
’1’
’0’
’1’
’0’
t
double word read access
Data Sheet
RDmin
·
t
t
DRDZ
permanently high
RD
/CS
/BE0
’1’
’0’
’1’
’1’
’1’
’0’
’1’
’0’
data
data
µ
’0’
Data access
no access
byte access on AD[7:0]
byte access on AD[15:8]
byte access on AD[23:16]
byte access on AD[31:24]
word access on AD[15:0]
word access on AD[31:16]
double word access
t
DRDH
-counter read access have 8 bit, 16 bit or
and
t
CYCLE
/WR
double word read access
t
RDmin
t
’1’
t
DRDZ
RD
data
data
Cologne
Chip
t
DRDH
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