MPC8548E Freescale, MPC8548E Datasheet - Page 124

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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Clocking
19.2
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform
clock. The frequency of the CCB is set using the following reset signals, as shown in
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB
frequency must equal the DDR data rate.
For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.
124
Memory bus clock speed
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
Binary Value of LA[28:31] Signals CCB:SYSCLK Ratio Binary Value of LA[28:31] Signals CCB:SYSCLK Ratio
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
settings.
•
•
SYSCLK input signal
Binary value on LA[28:31] at power up
CCB/SYSCLK PLL Ratio
0000
0001
0010
0011
0100
0101
0110
0111
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Characteristic
Table 75. Memory Bus Clocking Specifications (MPC8543E)
Section 19.2, “CCB/SYSCLK PLL Ratio,”
Reserved
Reserved
Table 76. CCB Clock Ratio
16:1
2:1
3:1
4:1
5:1
6:1
Maximum Processor Core Frequency
Min
166
800, 1000 MHz
and
1000
1001
1010
1011
1100
1101
1110
1111
Section 19.3, “e500 Core PLL Ratio,”
Max
200
Freescale Semiconductor
Table
MHz
Unit
Reserved
Reserved
Reserved
76:
10:1
12:1
20:1
8:1
9:1
for ratio
Notes
1, 2