MPC8548E Freescale, MPC8548E Datasheet - Page 57

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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14.2
This section describes the general AC timing parameters of the PCI/PCI-X bus. Note that the clock
reference CLK is represented by SYSCLK when the PCI controller is configured for asynchronous mode
and by PCIn_CLK when it is configured for asynchronous mode.
Table 47
Figure 35
Freescale Semiconductor
CLK to output valid
Output hold from CLK
CLK to output high impedance
Input setup to CLK
Input hold from CLK
REQ64 to HRESET
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
3. All PCI signals are measured from OV
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
5. Input timings are measured at the pin.
6. The timing parameter t
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter t
9. The reset assertion timing requirement for HRESET is 100 μs.
10.Guaranteed by characterization.
11.Guaranteed by design.
inputs and t
timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, t
(K) going to the high (H) state or setup time. Also, t
reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
for 3.3-V PCI signaling levels.
through the component pin is less than or equal to the leakage current specification.
system clock period must be kept within the minimum and maximum defined ranges. For values see
Specifications .
provides the PCI AC timing specifications at 66 MHz.
PCI/PCI-X AC Electrical Specifications
provides the AC test load for PCI and PCI-X.
(first two letters of functional block)(reference)(state)(signal)(state)
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
9
setup time
Parameter
SYS
PCRHFV
Output
indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
Table 47. PCI AC Timing Specifications at 66 MHz
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
DD
Figure 35. PCI/PCI-X AC Test Load
/2 of the rising edge of SYSCLK or PCI_CLK n to 0.4 × OV
Z
0
= 50 Ω
PCRHFV
symbolizes PCI/PCI-X timing (PC) with respect to the time hard
Symbol
t
t
t
t
t
t
t
t
PCKHOV
PCKHOX
PCKHOZ
PCRVRH
PCRHRX
PCRHFV
PCIVKH
PCIXKH
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
1
R
L
10 × t
= 50 Ω
Min
2.0
3.0
10
—
—
0
0
SYS
LV
DD
PCIVKH
Max
/2
6.0
14
50
—
—
—
—
—
DD
symbolizes PCI/PCI-X
of the signal in question
Section 19,
clocks
clocks
Unit
ns
ns
ns
ns
ns
ns
SYS
, reference
“Clocking.”
PCI/PCI-X
2, 4, 11
2, 5, 10
2, 5, 10
6, 7, 11
Notes
2, 10
7, 11
8, 11
2, 3
for
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