MPC8548E Freescale, MPC8548E Datasheet - Page 18

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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RESET Initialization
5
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8548E.
component(s).
Table 9
18
Required assertion time of HRESET
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET negation
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
Maximum valid-to-high impedance time for actively driven POR configs with
respect to negation of HRESET
Note:
1. SYSCLK is the primary clock input for the MPC8548E.
Core and platform PLL lock times
Local bus PLL lock time
PCI/PCI-X bus PLL lock time
RESET Initialization
provides the PLL lock times.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Table 8
Parameter/Condition
provides the RESET initialization AC timing specifications for the DDR SDRAM
Parameter/Condition
Table 8. RESET Initialization Timing Specifications
Table 9. PLL Lock Times
Min
100
100
—
3
4
2
Min
—
—
—
Max
—
—
—
—
—
5
Freescale Semiconductor
Max
100
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
50
50
Unit
μs
μs
Notes
Unit
μs
μs
μs
—
—
1
1
1
1