MPC8548E Freescale, MPC8548E Datasheet - Page 97

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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25.These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ) to OV
26.Independent supplies derived from board V
27.Recommend a pull-up resistor (~1 kΩ) be placed on this pin to OV
29. The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], TSEC4_TXD3/TSEC3_TXD7,
30.This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively
31.This pin is only an output in eTSEC3 FIFO mode when used as Rx flow control.
32.These pins should be connected to XV
33.TSEC2_TXD1, TSEC2_TX_ER are multiplexed as cfg_dram_type[0:1]. They must be valid at power-up, even before
34.These pins should be pulled to ground through a 300-Ω (±10%) resistor.
35.When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled
36.MDIC0 is grounded through an 18.2-Ω precision 1% resistor and MDIC1 is connected to GV
38.These pins should be left floating.
39. If PCI1 or PCI2 is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI1_CLK or PCI2_CLK.
40.These pins should be connected to GND.
101.This pin requires an external 4.7-kΩ resistor to GND.
102.For Rev. 2.x silicon, DMA_DACK[0:1] must be 0b11 during POR configuration; for rev. 1.x silicon, the pin values during POR
103.If these pins are not used as GPIN n (general-purpose input), they should be pulled low (to GND) or high (to LV
104.These should be pulled low to GND through 2–10 kΩ resistors if they are not used.
105.These should be pulled low or high to LV
106.For rev. 2.x silicon, DMA_DACK[0:1] must be 0b10 during POR configuration; for rev. 1.x silicon, the pin values during POR
107.For rev. 2.x silicon, DMA_DACK[0:1] must be 0b01 during POR configuration; for rev. 1.x silicon, the pin values during POR
108.For rev. 2.x silicon, DMA_DACK[0:1] must be 0b11 during POR configuration; for rev. 1.x silicon, the pin values during POR
109.This is a test signal for factory use only and must be pulled down (100 Ω – 1 kΩ) to GND for normal machine operation.
110.These pins should be pulled high to OV
111.If these pins are not used as GPIN n (general-purpose input), they should be pulled low (to GND) or high (to OV
112.This pin must not be pulled down during POR configuration.
113.These should be pulled low or high to OV
HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.
driven.
HRESET assertion.
down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCI n _AD pins as ‘
connect’ or terminated through 2–10 kΩ pull-up resistors with the default of internal arbiter if the PCI n _AD pins are not
connected to any other PCI device. The PCI block will drive the PCI n _AD pins if it is configured to be the PCI arbiter—through
POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is
any other PCI device connected on the bus.
1% resistor. These pins are used for automatic calibration of the DDR IOs.
Otherwise the processor will not boot up.
configuration are don’t care.
2–10 kΩ resistors.
configuration are don’t care.
configuration are don’t care.
configuration are don’t care.
2–10 kΩ resistors.
Signal
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Table 66. MPC8548E Pinout Listing (continued)
DD
DD
.
DD
DD
DD
through 2–10 kΩ resistors.
through 2–10 kΩ resistors if they are not used.
.
through 2–10 kΩ resistors.
Package Pin Number
DD
.
DD
Pin Type
for normal machine operation.
DD
through an 18.2-Ω precision
Supply
Package Description
Power
DD
DD
) through
) through
Notes
no
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