MPC8548E Freescale, MPC8548E Datasheet - Page 140

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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Document Revision History
140
Revision
2
1
0
04/2008
10/2007
07/2007
Date
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
• Removed 1:1 support on
• Removed MDM from
•
•
• Split
• Adjusted maximum SYSCLK frequency down in
• Clarified notes to
• Added
• Clarified descriptions and added PCI/PCI-X to
• Removed support for 266 and 200 Mbps data rates per device erratum GEN-13 in
• Clarified Note 4 of
• Clarified the reference clock used in
• Corrected V
• Corrected V
• Removed DC parameters from
• Corrected V
• Corrected t
• Updated parameter descriptions for t
• Updated parameter descriptions for t
• Added LUPWAIT signal to
• Added LGTA signal to
• Corrected LUPWAIT assertion in
• Clarified the PCI reference clock in
• Added
• Added PBGA thermal information in
• Updated.”
• Updated
• Initial Release
Figure 56, “PLL Power Supply Filter Circuit with PLAT
Figure 57, “PLL Power Supply Filter Circuit with CORE
Supply Filter Circuit”) into three figures: the original (now specific for AVDD_PCI/AVDD_LBIU) and two
new ones.
device erratum GEN-13.
DDR2
Characteristics.”
Table
Timing Parameters (BV
(BV
Timing Parameters—PLL
and t
Signals (PLL Bypass
Full
DD
Lid.”
Figure 58, “PLL Power Supply Filter Circuit with PCI/LBIU
LBIXKH2
33, and
SDRAM.”
Section 4.4, “PCI/PCI-X Reference Clock
= 2.5 V)—PLL
Section 17.1, “Package
Table 83. Document Revision History (continued)
Table 82, “Part Numbering
MDC
IH
IL
IH
.
(max) in
(min) in
(min) in
Table
(min) in
Table 6, “EC_GTX_CLK125 AC Timing
Table 18, “DDR SDRAM Output AC Timing
34.
Table 17, “DDR SDRAM Input AC Timing
Mode).”
Enabled.”
Table 21, “GMII, MII, RMII, and TBI DC Electrical
Table 35, “MII Management DC Electrical
Table 22, “GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical
Figure
DD
Table 36, “MII Management AC Timing
Table 77, “e500 Core to CCB Clock
Bypassed.” Note that t
= 3.3 V)—PLL
Figure 23, “Local Bus Signals (PLL
25,
Parameters.”
Table
Figure
Figure 26
Section 14.2, “PCI/PCI-X AC Electrical
Nomenclature.”
Section 7.2, “DUART AC Electrical
Section 20.2, “Thermal for Version 2.1.1 Silicon FC-PBGA with
LBIVKH1
LBIVKH1
Substantive Change(s)
23,
26,
Table
Enabled” and
and
, t
, t
Figure 27
LBIVKH2
LBIVKL2
Table 9, “PLL Lock
24,
LBIVKL2
Figure
Table 5, “SYSCLK AC Timing
Timing.”
Table
, t
, t
Pins” (AVDD_PLAT).
and
LBIXKH1
Pins” (AVDD_CORE).
28.
LBIXKH1
Table 40, “Local Bus Timing Parameters
and t
25,
Specifications.”
Figure
Table
LBIXKL2
Ratio.”
Specifications.”
, and t
Enabled)” and
Pins,” (formerly called just “PLL Power
Specifications.”
, and t
Specifications.” MDM is an Output.
Characteristics.”
Times.”
28.
26,
were previously labeled t
LBIXKL2
LBIXKH2
Table
Characteristics.”
Specifications.”
Specifications”
27,
Freescale Semiconductor
in
in
Figure 24, “Local Bus
Specifications” per
Table 41, “Local Bus
Table 39, “Local Bus
Table
Section 6, “DDR and
28,
Table
LBIVKH2
31,