MPC8548E Freescale, MPC8548E Datasheet - Page 45

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

www.DataSheet4U.com
Figure 23
Table 41
Freescale Semiconductor
Local bus cycle time
Local bus duty cycle
Internal launch/capture clock to LCLK delay
Input setup to local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition (LATCH hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
LA[27:31]/LBCTL/LBCKE/LOE/
describes the timing parameters of the local bus interface at BV
LSDA10/LSDWE/LSDRAS/
through
Output (Address) Signal:
LSDCAS/LSDDQM[0:3]
Output (Data) Signals:
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
Figure 28
Output Signals:
Input Signals:
Input Signal:
LSYNC_IN
LUPWAIT
LAD[0:31]
Table 41. Local Bus Timing Parameters—PLL Bypassed
Parameter
LGTA
LALE
show the local bus signals.
Figure 23. Local Bus Signals (PLL Enabled)
t
t
LBKHOV1
LBKHOV2
t
LBKHOV3
t
LBKHOV4
t
t
t
t
t
LBIVKH1
LBIVKH2
LBKHOX1
LBKHOX2
LBKHOX2
t
t
t
LBKHOZ1
LBKHOZ2
LBKHOZ2
t
LBOTOT
t
Symbol
LBKH/
t
t
t
t
t
t
t
LBKLOV1
LBIVKH1
LBIXKH1
LBIVKL2
LBIXKL2
LBKHKT
LBOTOT
t
LBK
t
LBK
1
DD
t
–1.8
–1.3
t
Min
2.3
6.2
6.1
1.5
LBIXKH1
LBIXKH2
12
43
—
= 3.3 V with PLL disabled.
Max
–0.3
4.4
57
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
%
Local Bus
Notes
4, 5
4, 5
4, 5
4, 5
—
—
2
8
6
45