MPC8548E Freescale, MPC8548E Datasheet - Page 136

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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Ordering Information
Pins V28 and M26 must be tied to XV
resistor.
21.11 Guideline for PCI Interface Termination
PCI termination if PCI 1 or PCI 2 is not used at all.
Option 1
If PCI arbiter is enabled during POR:
Option 2
If PCI arbiter is disabled during POR:
21.12 Guideline for LBIU Termination
If the LBIU parity pins are not used, the following is the termination recommendation:
22 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 22.1, “Part Numbers Fully Addressed by this Document.”
22.1
Table 82
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
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All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating.
All PCI control pins can be grouped together and tied to OV
It is optional to disable PCI block through DEVDISR register after POR reset.
All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied
to OV
All PCI control pins can be grouped together and tied to OV
It is optional to disable PCI block through DEVDISR register after POR reset.
For LDP[0:3]—tie them to ground or the power supply rail via a 4.7-kΩ resistor.
For LPBSE—tie it to the power supply rail via a 4.7-kΩ resistor (pull-up resistor).
provides the Freescale part numbering nomenclature for the MPC8548E. Note that the individual
Part Numbers Fully Addressed by this Document
DD
It is recommended to power down the unused lane through SRDSCR1[0:7]
register (offset = 0xE_0F08) (this prevents the oscillations and holds the
receiver output in a fixed state) that maps to SERDES lane 0 to lane 7
accordingly.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
through a single (or multiple) 10-kΩ resistor(s).
DD
. Pins V27 and M25 must be tied to GND through a 300-Ω
NOTE
DD
DD
through a single 10-kΩ resistor.
through a single 10-kΩ resistor.
Freescale Semiconductor