MPC8548E Freescale, MPC8548E Datasheet - Page 80

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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Serial RapidIO
For each baud rate at which an LP-serial transmitter is specified to operate, the output eye pattern of the
transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown
in
the device is driving a 100-Ω ± 5% differential resistive load. The output eye pattern of an LP-serial
transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need
only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized.
80
Output voltage
Differential output voltage
Deterministic jitter
Total jitter
Multiple output skew
Unit interval
Output voltage
Differential output voltage
Deterministic jitter
Total jitter
Multiple output skew
Unit interval
Figure 52
Characteristic
Characteristic
with the parameters specified in
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Table 59. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Table 58. Long Run Transmitter AC Timing Specifications—2.5 GBaud
Symbol
Symbol
V
V
DIFFPP
DIFFPP
S
S
V
V
J
J
UI
J
J
UI
MO
MO
D
D
O
T
O
T
–0.40
–0.40
Min
800
400
Min
800
320
—
—
—
—
—
—
Range
Range
Table 60
1600
1000
1600
1000
Max
2.30
0.17
0.35
Max
2.30
0.17
0.35
400
320
when measured at the output pins of the device and
mVp-p
mVp-p
UI p-p
UI p-p
UI p-p
UI p-p
Unit
Unit
ps
ps
ps
ps
V
V
Voltage relative to COMMON of either signal
comprising a differential pair
Skew at the transmitter output between lanes of a
multilane link
±100 ppm
Voltage relative to COMMON of either signal
comprising a differential pair
Skew at the transmitter output between lanes of a
multilane link
±100 ppm
Notes
Notes
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Freescale Semiconductor