MPC8548E Freescale, MPC8548E Datasheet - Page 63

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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15.2.2
The DC level requirement for the MPC8548E SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below:
Freescale Semiconductor
•
•
•
The input amplitude requirement:
— This requirement is described in detail in the following sections.
Differential mode
— The input amplitude of the differential clock must be between 400 and 1600 mV differential
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the
Single-ended mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
— The SD_REF_CLK input average voltage must be between 200 and 400 mV.
peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of
the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV.
This requirement is the same for both external DC-coupled or AC-coupled connection.
Receiver Characteristics,”
average voltage (common mode voltage) to be between 100 and 400 mV.
SerDes reference clock input requirement for DC-coupled connection scheme.
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn).
input requirement for AC-coupled connection scheme.
(single-ended swing) must be between 400 and 800 mV peak-to-peak (from V
SD_REF_CLK either left unconnected or tied to ground.
the SerDes reference clock input requirement for single-ended signaling mode.
DC Level Requirement for SerDes Reference Clocks
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Figure 39. Receiver of SerDes Reference Clocks
SD_REF_CLK
SD_REF_CLK
the maximum average current requirements sets the requirement for
50 Ω
50 Ω
Figure 41
Input
Amp
Section 15.2.1, “SerDes Reference Clock
shows the SerDes reference clock
High-Speed Serial Interfaces (HSSI)
Figure 40
min
Figure 42
to V
shows the
max
shows
) with
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