MPC8548E Freescale, MPC8548E Datasheet - Page 43

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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Table 40
Freescale Semiconductor
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
6. t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[ n ]. Skew measured between
8. Guaranteed by design.
Local bus cycle time
Local bus duty cycle
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LGTA/UPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition (LATCH hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one (1). Also, t
the output (O) going invalid (X) or output hold time.
bypass mode to 0.4 × BV
through the component pin is less than or equal to the leakage current specification.
programmed with the LBCR[AHD] parameter.
complementary signals at BV
LBOTOT
describes the timing parameters of the local bus interface at BV
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
(first two letters of functional block)(reference)(state)(signal)(state)
Table 39. Local Bus Timing Parameters (BV
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Table 40. Local Bus Timing Parameters (BV
LBKHOX
DD
Parameter
Parameter
symbolizes local bus timing (LB) for the t
of the signal in question for 3.3-V signaling levels.
DD
/2.
DD
/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
DD
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
= 3.3 V)—PLL Enabled (continued)
LBK
LBK
DD
t
Symbol
Symbol
t
t
t
t
t
t
LBKH/
t
t
LBKSKEW
t
t
t
t
clock reference (K) to go high (H), with respect to
LBKHOZ2
t
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
LBKHOX2
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBOTOT
clock reference (K) goes high (H), in this case for
= 2.5 V)—PLL Enabled
t
LBK
t
LBK
1
1
DD
Min
Min
7.5
1.9
1.8
1.1
1.1
1.5
0.8
0.8
—
43
—
—
—
—
—
= 2.5 V.
LBIXKH1
Max
Max
150
2.5
2.1
2.3
2.4
2.4
12
57
—
—
—
—
—
—
—
symbolizes local bus
LBOTOT
Unit
Unit
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
is
Local Bus
Notes
Notes
7, 8
3, 4
3, 4
3, 4
3, 4
for
—
—
5
2
6
3
3
3
3
3
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