MPC8548E Freescale, MPC8548E Datasheet - Page 130

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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System Design Information
21.4
The SerDes block requires a clean, tightly regulated source of power (SV
jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
21.5
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to V
required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must
remain unconnected. Power and ground connections must be made to all external V
OV
21.6
The MPC8548E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins
including I
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
The following pins must not be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1], and TEST_SEL/
TEST_SEL pins must be set to a proper state during POR configuration. Refer to the pinlist table of the
individual device for more details
Refer to the PCI 2.2 specification for all pull ups required for PCI.
130
DD
•
•
•
, GV
First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SV
XV
supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
Connection Recommendations
SerDes Block Power Supply Decoupling Recommendations
Pull-Up and Pull-Down Resistor Requirements
2
DD
DD
C pins and PIC (interrupt) pins.
) to the board ground plane on each side of the device. This should be done for all SerDes
, LV
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Figure
DD
, and GND pins of the device.
62. Care must be taken to ensure that these pins are maintained at a valid deasserted
DD
, TV
DD
, BV
DD
, OV
DD
and XV
DD
, GV
DD
Freescale Semiconductor
DD
DD
, TV
) to ensure low
, and LV
DD
DD
, BV
and
DD
DD
, as
,