MPC8548E Freescale, MPC8548E Datasheet - Page 139

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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23 Document Revision History
Table 83
Freescale Semiconductor
Revision
4
3
provides a revision history for the MPC8548E hardware specification.
04/2009
01/2009
Date
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
• In
• In
• In
• Modified
• Modified DDR clk rate min from 133 to 166 MHz.
• Modified note in
• In
• In
• Modified
• Added a note on
• In
• Added note to
•
• In
•
•
• In
• In
• In
• In
• In
• In
• In
• In
• In
• Added new section,
•
•
• Added information to
•
•
moved text, “MII management voltage” from LV
OVDD row of input voltage section.
time.
OV
column, and changed all instances of “LO” to “L0.” In addition, added note 8.
and in note 3, changed “TRX-EYE-MEDIAN-to-MAX-JITTER,” to “T
frequency is less than 1200 MHz
Pinout
[Section 4.6, “Platform Frequency Requirements for PCI-Express and Serial RapidIO.”
minimum frequency equation to be 527 MHz for PCI x8.
Section 4.5, “Platform to FIFO Restrictions.”
Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics.”
and add ‘or 2.5 V’ after 3.3 V.
TSEC n _TX_CLK.
high from 32 to 48 ns.
Section 16.1, “DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK.”
paragraph.
Section 17.1, “DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK.”
paragraph.
Section 21.3, “Decoupling Recommendations.”
Table 82, “Part Numbering Nomenclature.”
Table 52,
Table
Table
Table
Table 51,
Table 66,
Table
Table
Table 23
Table
Table
Table 29
Section 8.2.5, “TBI Single-Clock Mode AC Specifications.”
Table
Table
Table
DD
.
ListingTable 69,
1, “Absolute Maximum Ratings
5, “SYSCLK AC Timing Specifications,” added notes 7 and 8 to SYSCLK frequency and cycle
35, “MII Management DC Electrical Characteristics,” changed all instances of LV
5, added note 7.
22, modified table title to include GMII, MII, RMII, and TBI.
24, added a note.
25,
33,
35, changed all instances of OV
36, “MII Management AC Timing Specifications,” changed MDC minimum clock pulse width
Section 15, “High-Speed Serial Interfaces
Table
and
and
“Differential Receiver (RX) Input Specifications,” modified equations in Comments column,
“Differential Transmitter (TX) Output Specifications,” modified equations in Comments
“MPC8548E Pinout
Table
Table
Table
78, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”
Table
Figure
Table 83. Document Revision History
Table
Section 4.1, “System Clock
26,
34,
Section 15, “High-Speed Serial Interfaces (HSSI).”
78, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”
Figure
24, changed clock period minimum to 5.3.
Table
Figure
70, “Processor Core Clocking Specifications (MPC8548E and MPC8547E), “.”
15, changed all instances of PMA to TSEC n .
“MPC8543E Pinout Listing,” added note 5 to LA[28:31].
27,
63, both in figure and in note.
18, and
Table
ListingTable 67,
Substantive Change(s)
Figure
28, and
1
DD
,” and in
In Silicon Version column added Ver. 2.1.2.
to LV
Changed platform clock frequency to 4.2.
20, changed all instances of REF_CLK to
Timing,” to limit the SYSCLK to 100 MHz if the core
Table
DD
Modified the recommendation.
“MPC8547E Pinout
DD
Table
/TV
/TV
(HSSI),” to reflect that there is only one SerDes.
29, removed subtitle from table title.
DD
DD
2, “Recommended Operating Conditions,”
to OV
.
Replaced first paragraph.
DD
, added “Ethernet management” to
RX-EYE-MEDIAN-to-MAX-JITTER
ListingTable 68,
Document Revision History
Added MII after GMII
“MPC8545E
Added new
Changed
Added new
DD
/OV
.”
DD
to
139