MPC8548E Freescale, MPC8548E Datasheet - Page 71

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

www.DataSheet4U.com
16.4.2
The TX eye diagram in
Figure
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level
of the de-emphasized bit will always be relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
Freescale Semiconductor
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in
3. A T
4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
5. Measured between 20%–80% at transmitter package pins into a test load as shown in
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a.
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a.
8. MPC8548E SerDes transmitter does not have CTX built in. An external AC coupling capacitor is required.
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in
transmitter collected over any 250 consecutive TX UIs. The T
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and
D– line (that is, as measured by a vector network analyzer with 50-Ω probes—see
C
TX
Z
TX-EYE
L
TX-DIFF-DC
T
Symbol
is optional for the return loss measurement.
Z
TX-SKEW
50) in place of any real PCI Express interconnect +RX component.
crosslink
TX-DC
C
TX
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
Transmitter Compliance Eye Diagrams
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Table 51. Differential Transmitter (TX) Output Specifications (continued)
random timeout
Transmitter DC
TX impedance
DC differential
Lane-to-lane
output skew
AC coupling
Parameter
impedance
Crosslink
capacitor
Figure 48
is specified using the passive compliance/test measurement load (see
Min
80
40
75
—
0
Nom
100
—
—
—
—
+ 2 UI
Max
120
500
200
—
TX-EYE-MEDIAN-to-MAX-JITTER
1
Unit
ms
ps
nF
Ω
Ω
TX DC differential mode low impedance
Required TX D+ as well as D– DC impedance
during all states
Static skew between any two transmitter lanes
within a single Link
All transmitters shall be AC coupled. The AC
coupling is required either within the media or
within the transmitting component itself. See note
8.
This random timeout helps resolve conflicts in
crosslink configuration by eventually resulting in
only one downstream and one upstream port.
See Note 7.
Figure
Figure 50
50). Note that the series capacitors
median is less than half of the total
TX-JITTER-MAX
Comments
Figure
Figure 50
for both V
48.)
and measured over
= 0.30 UI for the
TX-D+
and V
PCI Express
TX-D–
71
.