MPC8548E Freescale, MPC8548E Datasheet - Page 66

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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High-Speed Serial Interfaces (HSSI)
Figure 45
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
the MPC8548E SerDes reference clock input’s DC requirement, AC-coupling has to be used.
assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL
outputs prior to AC-coupling. Its value could be ranged from 140 to 240 Ω depending on the clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8548E SerDes
reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak).
For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock
input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Consult a
clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular
clock driver chip.
66
LVPECL CLK Driver Chip
LVDS CLK Driver Chip
Clock Driver
Clock Driver
Clock Driver
Clock Driver
Clock Driver
Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
CLK_Out
CLK_Out
CLK_Out
CLK_Out
CLK_Out
CLK_Out
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
10 nF
10 nF
R1
R1
100 Ω Differential PWB Trace
100 Ω Differential PWB Trace
R2
R2
R2
R2
10 nF
10 nF
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
50 Ω
50 Ω
50 Ω
50 Ω
Freescale Semiconductor
SerDes Refer.
CLK Receiver
SerDes Refer.
CLK Receiver
MPC8548E
MPC8548E
Figure 45