MPC8548E Freescale, MPC8548E Datasheet - Page 15

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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4.2
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then
used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter
specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB
clock. That is, minimum clock high time is 2 × t
no minimum RTC frequency; RTC may be grounded if not needed.
Freescale Semiconductor
At recommended operating conditions (see
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow
6. This parameter has been adjusted slower according to the workaround for device erratum GEN 13.
7. For spread spectrum clocking. Guidelines are + 0% to –1% down spread at modulation rate between 20 and 60 kHz on
8. System with operating core frequency less than 1200 MHz must limit SYSCLK frequency to 100 MHz maximum..
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies.Refer to
settings.
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
SYSCLK.
Real Time Clock Timing
Parameter/Condition
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Table 5. SYSCLK AC Timing Specifications (continued)
Section 19.2, “CCB/SYSCLK PLL Ratio,”
Table
2) with OV
t
KHK
Symbol
t
KH
/t
—
SYSCLK
, t
CCB
KL
DD
, and minimum clock low time is 2 × t
= 3.3 V ± 165 mV
Min
0.6
40
—
and
Section 19.3, “e500 Core PLL Ratio,”
.
Typ
1.0
—
—
± 150
Max
1.2
60
Unit
CCB
ns
ps
%
. There is
Input Clocks
for ratio
Notes
4, 5
2
3
15