MPC8548E Freescale, MPC8548E Datasheet - Page 62

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (current mode logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or
TD) is 500 mVp-p, which is referred as the single-ended swing for each signal. In this example, since the
differential signaling environment is fully symmetrical, the transmitter output’s differential swing (V
has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between
500 and –500 mV, in other words, V
differential voltage (V
15.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and
SD_REF_CLK for PCI Express and serial RapidIO.
The following sections describe the SerDes reference clock requirements and some application
information.
15.2.1
Figure 39
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The supply voltage requirements for XV
SerDes Reference clock receiver reference circuit structure:
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
The maximum average current requirement that also determines the common mode voltage range:
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 Ω to
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks.
in
termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
differential mode and single-ended mode description below for further detailed requirements.
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V), such that
each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
must be AC-coupled off-chip.
SerDes Reference Clock Receiver Characteristics
Figure
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
39. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω
DIFFp
) is 500 mV. The peak-to-peak differential voltage (V
OD
is 500 mV in one phase and –500 mV in the other phase. The peak
DD_SRDS2
are specified in
Table 1
DIFFp-p
and
Freescale Semiconductor
Table
) is 1000 mVp-p.
2.
OD
)