MPC8548E Freescale, MPC8548E Datasheet - Page 14

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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Power Characteristics
3
The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this
family of PowerQUICC III devices is shown in
4
4.1
Table 5
14
At recommended operating conditions (see
SYSCLK frequency
SYSCLK cycle time
Notes:
1. CCB frequency is the SoC platform frequency, which corresponds to the DDR data rate.
2. SLEEP is based on V
3. Typical-65 is based on V
4. Typical-105 is based on V
5. Maximum is based on V
Power Characteristics
Input Clocks
CCB Frequency
provides the system clock (SYSCLK) AC timing specifications for the MPC8548E.
System Clock Timing
Parameter/Condition
400
500
533
In order to guarantee MCKE low during power-up, the above sequencing for
GV
in an indeterminate state during power-up, then the sequencing for GV
not required.
From a system standpoint, if any of the I/O power supplies ramp prior to the
V
one or zero during power-up, and extra current may be drawn by the device.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
DD
DD
core supply, the I/Os associated with that I/O supply may drive a logic
1
is required. If there is no concern about any of the DDR signals being
Core Frequency
DD
DD
DD
= 1.1 V, T
1000
1200
1500
1333
DD
800
Table 5. SYSCLK AC Timing Specifications
= 1.1 V, T
= 1.1 V, T
= 1.1 V, T
Table 4. MPC8548E Power Dissipation
Table
j
= 65°C.
j
j
= 105°C, running a smoke test.
= 65°C, running Dhrystone.
j
2) with OV
= 105°C, running Dhrystone.
SLEEP
11.5
Symbol
2.7
2.7
2.7
6.2
t
f
SYSCLK
SYSCLK
Table
2
NOTE
NOTE
DD
= 3.3 V ± 165 mV
Typical-65
4.
13.6
4.6
5.0
5.4
7.9
Min
7.5
16
3
Typical-105
.
16.5
10.8
Typ
7.5
7.9
8.3
—
—
4
Maximum
Max
133
60
18.6
12.8
8.1
8.5
8.9
Freescale Semiconductor
DD
5
is
MHz
Unit
ns
Unit
W
W
W
W
1, 6, 7, 8
6, 7, 8
Notes