LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 120

• Manufacturer Part Number: LM3S2965-IQC20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Hibernation Module
7.1
7.2
7.2.1
120
Block Diagram
Figure 7-1. Hibernation Module Block Diagram
Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off. The Hibernation module itself is powered from a separate
supply such as a battery or auxillary supply. It also has a separate clock source to maintain a
real-time clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn
back on the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a
certain value. The Hibernation module can also detect when the battery voltage is low, and optionally
prevent hibernation when this occurs.
Power-up from a power cut to code execution is defined as the regulator turn-on time (specifed at
250 μs maximum) plus the normal chip POR (see Figure 23-11 on page 534).
Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is t
must guarantee that a delay of t
Hibernation registers, or between a write followed by a read to those same registers. There is no
restriction on timing for back-to-back reads from the Hibernation module. Refer to “Register
Descriptions” on page 124 for details about which registers are subject to this timing restriction.
XOSC0
XOSC1
WAKE
VDD
VBAT
HIBCTL.CLKSEL
HIBCTL.CLK32EN
Non-Volatile
HIBDATA
Memory
/128
HIBCTL.LOWBATEN
HIB_REG_WRITE
Preliminary
RTC
Low Battery
Pre-Divider
HIBRTCLD
HIBRTCM0
HIBRTCM1
HIBRTCC
HIBRTCT
Detect
is inserted between back-to-back writes to certain
HIBCTL.PWRCUT
HIBCTL.RTCWEN
HIBCTL.EXTWEN
HIBCTL.VABORT
MATCH0/1
LOWBAT
HIB_REG_WRITE
Sequence
HIBIM
HIBRIS
HIBMIS
HIBIC
Interrupts
Power
Logic
, therefore software
June 04, 2007
Interrupts
to CPU
HIB